1. Field of the Invention
This invention relates to semiconductor memory devices and methods of reading data therefrom. More particularly, the invention relates to a semiconductor memory device having an improved reading system and to a method of reading data therefrom.
2. Description of the Background Art
This invention is applicable to both single port memories and multi-port memories. Disadvantages of the prior art will be described hereinafter with reference mainly to a dual port memory which is one example of multi-port memories.
FIG. 5 is a block diagram showing an example of use modes of the dual port memory. In the drawing, a dual port memory 1 has two input/output ports. One input/output port (hereinafter called "A port") is connected through a system bus 2 to a host system 3. The other port (hereinafter called "B port") of the dual port memory 1 is connected through a system bus 4 to a slave system 5. The host system 3 and slave system 5 may be any type as long as they are designed to process data. These systems are typically designed as multiprocessor systems including CPUs, for example. Thus, the host system 3 has a host CPU 31, ROMs 32 and RAMs 33, while the slave system 5 has a slave CPU 51, ROMs 52 and RAMs 53. The dual port memory 1 includes a built-in memory device. This memory device is separately accessible to the host system 3 and slave system 5.
The dual port memory 1 as described above is often used in data transfer between the host system 3 and slave system 5. Where the host system 3 and slave system 5 operate asynchronously, for example, it is difficult to transfer data directly between the two systems. The respective systems are capable of inputting or output data when necessary by data transfer through the dual port memory 1. This improves system throughput, and allows the two systems 3 and 5 to operate in relation to each other to realize a system configuration of increased scale.
FIG. 6 is a block diagram showing an example of known dual port memories. In the drawing, a memory cell array 10 includes a plurality of word lines and a plurality of bit lines arranged to cross each other, with a memory cell provided at the intersection of each word line and bit line. This memory cell array 10 has a decoder 11a and a sense amplifier 12a for the A port, and a decoder 11b and a sense amplifier 12b for the B port. The decoder 11a receives A-port address data from the host system 3 through an address input terminal 13a, while the decoder 11b receives B-port address data from the slave system 5 through an address input terminal 13b. A tri-state storage device 15a for data writing and a tri-state storage device 16a for data reading are connected in parallel between the sense amplifier 12a and an A-port data input/output terminal 14a. A write enable signal is applied from the host system 3 through an A-port write signal input terminal 17a to a control terminal of the tri-state storage device 15a. The tri-state storage device 15a has an output state controllable in response to this write enable signal. A read enable signal is applied from the host system 3 through an A-port read signal input terminal 18a to a control terminal of the tri-state storage device 16a. The tri-state storage device 16a has an output state controllable in response to the read enable signal. For the B port, similarly, a tri-state storage device 15b for data writing and a tri-state storage device 16b for data reading are connected in parallel between the sense amplifier 12b and a B-port data input/output terminal 14b. A write enable signal is applied from the slave system 5 through a B-port write signal input terminal 17b to a control terminal of the tri-state storage device 15b. The tri-state storage device 15b has an output state controllable in response to this write enable signal. A read enable signal is applied from the slave system 5 through a B-port read signal input terminal 18b to a control terminal of the tri-state storage device 16b. The tri-state storage device 16b has an output state controllable based on the read enable signal.
FIG. 7 is a view showing an input/output structure for one memory cell in the memory cell array 10 shown in FIG. 6. The memory cell array 10 has a plurality of memory cells 101 arranged in rows and columns to form a matrix. As shown in FIG. 7, the memory cell array 10 has two word lines 103a and 103b for each row of memory cells 101, and two bit lines 104a and 104b for each column. Further, two transfer gate transistors 102a and 102b are provided for each memory cell 101. The word line 103a, bit line 104a and transfer gate transistor 102a are associated with the A port. The word line 103b, bit line 104b and transfer gate transistor 102b are associated with the B port. In this way, the dual port memory shown in FIGS. 6 and 7 has completely independent access systems for the A port and the B port. Consequently, the host system 3 and slave system 5 are allowed to access the memory cell array 10 simultaneously.
With the dual port memory 1 having the above construction, the tri-state storage device 15a is activated when a write request is received from the host system 3, whereby writing data is applied from the host system 3 to the sense amplifier 12a. When a write request is received from the slave system 5, the tri-state storage device 15b is activated whereby writing data is applied from the slave system 5 to the sense amplifier 12b. When a read request is received from the host system 3, the tri-state storage device 16a is activated whereby data read from a selected memory cell is outputted to the host system 3 through the A-port data input/output terminal 14a. When a read request is received from the slave system 5, the tri-state storage device 16b is activated whereby a data read from a selected memory cell is outputted to the slave system 5 through the B-port data input/output terminal 14b.
Generally, it is necessary for the dual port memory to have two pairs of bit lines and word lines for each memory cell as shown in FIG. 7. As a result, the dual port memory has a large wiring capacitance and requires an access time nearly twice that of an ordinary ROM or RAM. It has therefore been conventional practice that, when configuring a system using a dual port memory, the ready function (standby function) of the CPU is used to realize a maximum speed from the system.
FIG. 8 shows a multiprocessor system using CPUs having the ready function. In the drawing, the host system 3 and slave system 5 include address decoders 34 and 54, respectively. The address decoder 34 decodes address data outputted to the system bus 2, and outputs a ready signal when the dual port memory 1 is accessed. Similarly, the address decoder 54 decodes address data outputted to the system bus 4, and outputs a ready signal when the dual port memory 1 is accessed. The ready signal outputted from the address decoder 34 is applied to a ready terminal (RDY terminal) of the host CPU 31, while the ready signal outputted from the address decoder 54 is applied to a ready terminal (RDY terminal) of the slave CPU 51. The host CPU 31 and slave CPU 51, when the ready signals are received from the address decoders 34 and 54, respectively, wait for a predetermined time before making access to the dual port memory 1.
FIG. 9 is a time chart illustrating operations of the multiprocessor systems shown in FIGS. 5 and 8. In FIGS. 9, (1) and (2) show the operation of the multiprocessor system shown in FIG. 8, while (3) and (4) show the operation of the multiprocessor system shown in FIG. 5.
First, the operation of the multiprocessor system shown in FIG. 8 will be described with reference to FIGS. 9 (1) and (2). FIG. 9 (1) shows cycles of a clock signal for operating the CPU 31 (or CPU 51). FIG. 9 (2) shows operating timing of the CPU 31 (or 51) for executing processes a-h. As shown in FIGS. 9 (1) and (2), the CPU 31 (or 51) operates in synchronism with the operating clock signal. For example, process for reading the ROMs 32 (or 52) and fetching a command is carried out in the first cycle of the operating clock signal. Process b for writing into the RAMs 33 (or 53) in accordance with the command fetched in the process a is carried out in the second cycle of the operating clock signal. What should be noted here is the operating timing for process f. Process f is a process for reading data from the dual port memory 1 in response to a command fetched in process e. As noted hereinbefore, the dual port memory 1 has a disadvantage of slow access speed since two word lines and two bit lines are provided for each memory cell. Consequently, process f for reading data from the dual port memory 1 requires a longer execution time than the other processes illustrated. In view of this drawback, the address decoder 34 (or 54) applies the ready signal to the CPU 31 (or 51) upon start of process f by the CPU 31 (or 51). This causes the CPU 31 (or 51) to wait for a predetermined time (a half cycle of the operating clock signal in FIG. 9 (2)) until completion of process f. As a result, the CPU 31 (or 51) is given a sufficient time for making a read access to the CPU 31 (or 51), thereby to read correct data from the dual port memory 1. Upon completion of process f, the CPU 31 (or 51) is freed from the standby and returns to the normal operating state.
The operation of the multiprocessor system shown in FIG. 5 will be described next with reference to FIGS. 9 (3) and (4). FIG. 9 (3) shows cycles of a clock signal for operating the CPU 31 (or CPU 51). FIG. 9 (4) shows operating timing of the CPU 31 (or 51) for executing processes a-h as in FIG. 9 (2). The CPU 31 (or 51) in the multiprocessor system shown in FIG. 5 does not possess the ready function of its counterpart in the multiprocessor system shown in FIG. 8. It is therefore impossible to prolong the execution time for process f alone for reading data from the dual port memory 1. In the multiprocessor system shown in FIG. 5, the time needed to execute process f is secured by means of the operating clock signal having cycles twice as long as those of the clock signal used in the multiprocessor system shown in FIG. 8. As a result, the time consumed in executing the processes other than process f doubles the time required by the multiprocessor system shown in FIG. 5.
As noted above, the execution time of each process is extended without avail in the multiprocessor system of FIG. 5 using the CPUs not having the ready function. Thus, the operating speed of the CPUs is not used to the full extent.
As described above, it is an effective measure to give CPUs the ready function in order to make full use of the operating speed of the CPUs. However, some of the CPUs used in one-chip microcomputers and the CPUs intended for special purposes are destitute of the ready function. Use of such CPUs requires a reduction in the frequency of the clock signal for operating the system, which poses the problem of reducing the operating speed performance of the entire system. This problem occurs with a single port memory as well as a multi-port memory having a plurality of ports. Where, for example, a single system uses a plurality of memories having different operating speeds, the above problem occurs between a memory of slow operating speed and the system.
In one way of constructing a multiprocessor system, a single processor system (e.g. a host system) is completed first and then a slave system designed to use part of the data in the host system is added to complete the whole multiprocessor system. In this case, as shown in FIG. 10, the slave system may be added without altering the program of the host system if addresses of the dual port memory are superposed on an address space 320 of memories inside the host system which are controlled by the host CPU 31 because this will not enlarge the address space of the memories that needs the control on the host system side.
However, it has been conventionally impossible to arrange the address regions of the dual port memory in a way to share the address space with the internal memories of the host system. The reason is that, when the host CPU 31 attempts to read data from the dual port memory, an internal memory region having the same address would also be designated, resulting in a collision of data.
Therefore, when the slave system is added to the completed host system, it is necessary to arrange the address regions of the dual port memory in a position outside of the address space of the internal memories of the host system. This requires a program for the host system to be designed all over again.
This problem will be described more specifically taking automobile engine control for example. Automobile engine control requires data of an engine control system to control the transmission in an automatic car. In a manual shift car such as a sports car or the like, however, transmission control may not be carried out by a microcomputer. That is, some of the automobiles having the same engine require transmission control by a microcomputer and others do not. When designing a microcomputer system for engine control which may or may not require a microcomputer for transmission control, different programs must be prepared for the case involving data transfer between the host system and dual port memory and for the case involving no such data transfer. This is an instance of doubled, irksome trouble, and tends to create a problem of management as well. Thus, the address regions of the dual port memory should be arranged on the address space in the system that uses the dual port memory, if possible.
In the prior art, as described above, where a system having a CPU without the ready function has access to a low-speed memory, the operating speed of the system must correspond the access speed of the memory. This results in lowering the operating speed performance of the system.
Where a plurality of systems share one multi-port memory, with the address regions of the multi-port memory superposed on the address space of the internal memories of one system, collision occurs between the data from the internal memories of the system and the data from the multi-port memory.